When a semiconductor memory device is fabricated, one defective cell out of numerous micro cells results in the semiconductor memory device being discarded as an inferior device because the semiconductor memory device will not be able to execute a sufficient level of performance as a memory. However, it is very inefficient yield-wise to discard the entire device for having few defective cells in the memory. Thus, redundancy cells, which are installed beforehand in the memory, are currently being used to perform a repair process for replacing the defective cells. In this way, yield is improved because the entire memory is resuscitated. The semiconductor memory device includes a fuse part which stores address information of defective cells in accordance with the connecting state of a fuse to perform the repair process.
FIG. 1A illustrates a plan view of a fuse part in a typical semiconductor device. FIG. 1B illustrates a cross-sectional view taken along a line A-A′ of the semiconductor device shown in FIG. 1A.
Referring to FIGS. 1A and 1B, a plurality of fuse lines 11 are formed over a semi-finished substrate 10. The fuse lines 11 are formed using one of existing circuit lines, e.g., plate lines and metal lines, in the fuse part rather than using additional lines.
An insulation layer 12 is formed over the fuse lines 11. The insulation layer 12 includes a fuse box 13 which represents a fuse open region. The fuse box 13 is formed by selectively etching the insulation layer 12. A portion of the insulation layer 12 remains to a certain thickness Rox over the fuse lines 11 after the fuse box 13 is formed.
According to the typical repairing method, a laser is applied to the fuse lines 11 through the fuse box 13 after forming the fuse part to cut the fuse lines 11. However, such repairing process shows the following limitations.
In order to successfully perform a fuse cutting process, the thickness Rox of the remaining insulation layer over the fuse lines has to be within appropriate range of values. However, the fuse cutting process often fails because it is difficult to control the thickness Rox due to the large differences in the thickness of the remaining insulation layer over the fuse lines formed over the wafer. Also, remnants are often generated after the fuse cutting process, causing limitations. Furthermore, damages may occur in fuse lines adjacent to the fuse lines being cut.